Arria 10 partial reconfiguration thru JTAG debug mode time out. No way to program the partial reconfiguration .rbf file. Please help!

​Hi John,

Thanks for quick response and it works! Please allow me to ask more questions related or somewhat related:

1. Why does the PR .rbf programming needs to lower the TCK frequency but regular .sof programming does not (it was using 24MHz programming .sof successfully).
2. Is the Intel FPGA devices' altera_reserved_tck the one connected to JTAG tck (just to confirm, though it looks it should be)? If so, what is the maximum frequency allowed in .sdc to constrain it?
3. For PR Controller configured as internal host, between using JTAG debug mode for PR programming and using PCIe thru PR Controller's Avalon Memory Mapped interface for PR programming, how fast will the PCIe thru PR Controller's Avalon Memory Mapped interface? Assuming the JTAG TCK is 6MHz and JTAG debug mode for PR programming speed is 1, for small PR persona, what is the speed ratio for PCIe thru PR Avalon vs JTAG debug mode for PR? And for large (very large) persona, what is the speed ration for PCIe thru PR Avalon vs JTAG debug mode for PR?

BTW, since it is an Intel support forum, welcome any other Intel FAEs to come to give answers too.

Thanks