Arria 10 Native Transceiver PHY 10GBASE-R w/KR FEC Clocks

Hi,

As I understand it, you have some inquiries related to the A10 Native PHY in 10GBaseR mode. Please see my responses as following:

1) Is the tx_pma_div_clkout destined to be used for my custom FPGA

fabric (MAC, data preprocessing, ...) and the tx_coreclkin?

[CP] Yes, your understanding is correct. This clock is of 156.25MHz which is to use with the XGMII interface and connect to xgmii_tx_clk/xgmii_rx_clk

2) Shall I activate the rx_pma_div_clkout to do the same here? If so,

why is it not activated by default?

[CP] You can use tx_pma_div_clkout for xgmii_tx/rx_clk. So, this clock is not used by default.

3) If the answers to 1) and 2) are yes, what is the purpose of the

tx_clkout and rx_clkout?

[CP] These are clocks used to clock in the internal blocks of the XCVR channels.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin