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Altera_Forum's avatar
Altera_Forum
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8 years ago

Arria 10 Hard IP Pcie Bar configurations

I want configure an endpoint AV memory mapped Pcie Hard Ip Gen2 x1 in a Qsys System. I need a suggestion as Bar blocks should be configured. I see an error bar0 size of 0 - bit is less than 4 a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The BAR has to be connected to something in Qsys and Qsys determines the BAR size from that. The BAR size cannot be set independently. If you want to export the BAR you can't do it directly. Export it through an Avalon-MM Pipeline Bridge. You can then set the address size parameter in the Bridge to indirectly set the BAR size.