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HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

Arria 10 GX Native PHY IP - Multiple protocols with Lane bonding requirements in a single TxR Bank

Hi, I am targeting Arria 10 GX 570 FPGA for custom protocol development using Transceivers. I am using Bank 1C primarily for PCie x2 (as this bank contains PCIe Hard IP). So PCIe will use channel...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.