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rled64's avatar
rled64
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Arria 10 EMIF writing to DDR4B data integrity issue

Hello dear community, I'm using development plateform based on Arria 10 device (HAN Pilot) for data acquisition (ADC) project. I have 16 samples of 16 bits incoming at a rate of 125 MHz (256bit wid...
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  • rled64's avatar
    rled64
    2 years ago

    Hello everyone,

    I found the issue, it was not related with the writing speed of 250MHz since 266MHz ref clock is only for EMIF reference clk, and it writes at 1066MHz.
    The issue apparently was some clock timing requirements which were not met. I had 2 external references clocks for my top level design (50MHz and 100MHz) which were not synchronous.

rled64's avatar
rled64
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello everyone,

I found the issue, it was not related with the writing speed of 250MHz since 266MHz ref clock is only for EMIF reference clk, and it writes at 1066MHz.
The issue apparently was some clock timing requirements which were not met. I had 2 external references clocks for my top level design (50MHz and 100MHz) which were not synchronous.