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Honored Contributor
Honored ContributorArria 10 DDR3 with Bank 3G and 3H
Hi all, I have a question about the bank usage for DDR3 memory in the Arria 10. I'm using the following hardware: Arria 10: 10AX115R3F40E2SG DDR3 memory: Micron MT41J128M16HA-187E:D ...
Altera_ForumHonored Contributor
Honored ContributorFor those remove pin, quartus will auto fit it to a location that meeting the fitting requirement.
Yes, your observation is expected. You have to use I/O lane that adjacent with each other. See Figure 93. I/O Bank Sharing of EMIF handbook https://www.altera.com/documentation/hco1416493470528.html#hco1416492629263 (This message was posted on behalf of Intel Corporation)
