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Rleduc's avatar
Rleduc
Icon for New Contributor rankNew Contributor
2 years ago
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Arria 10 - EMIF dual port access

Dear community, I am working on Arria 10 plateform (Terasic HAN Pilot) to perform acquisition from external ADC at 250MSPS - 16 bits. Until now, I had a small "On-chip memory" 50kB to temporarily s...
Memory
  • sstrell's avatar
    sstrell
    2 years ago

    Assuming you use Platform Designer to implement the design, arbitration logic for multiple hosts (masters) to access a single agent (slave) will be included in the interconnect.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Assuming you use Platform Designer to implement the design, arbitration logic for multiple hosts (masters) to access a single agent (slave) will be included in the interconnect.