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JPate3's avatar
JPate3
Icon for New Contributor rankNew Contributor
7 years ago
Solved

Are there specific rules about when the ready and valid signals can assert and deassert relative to each other on an Avalon Streaming Interface?

This entire question is in the context of an Avalon Streaming Interface where readLatency = 0 and readAllowance = 0. The AXI4-Stream specification explicitly states that: the master/source cannot ...
  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    7 years ago

    Hi,

    For readLatency = 0 and readAllowance = 0.

    ready signal need to be asserted before valid data-transfer, is the only requirement.

    1. Source can assert valid at any time.
    2. Sink can deassert ready at any time (after that slave can't capture the data).
    3. Sink captures the data from source only when ready = 1.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)

AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

For readLatency = 0 and readAllowance = 0.

ready signal need to be asserted before valid data-transfer, is the only requirement.

  1. Source can assert valid at any time.
  2. Sink can deassert ready at any time (after that slave can't capture the data).
  3. Sink captures the data from source only when ready = 1.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)