anyway to improve the reliability of triple SDI rx IP

How do you recover the clock?

1) Indeed, that input is not synchronous to any clock. Thus, you should not use set_input_constrains. What you should do is create a synchronized reset like this:

process(external_async_reset, clock) begin

if external_async_reset = '1'

internal_sync_reset <= '1'

elsif rising_edge(clk)

internal_sync_reset = '0';

end process;

You should then use internal_sync_reset as reset within your design, instead of external_async_reset.

You should also add a false path exception on all paths from external_async_reset.

set_false_path -from [get_ports external_async_reset]

2) Yes. You can create two derived clocks on that output clock pin, one for the 74.25 and another for the 148.5 MHz one. Then you can add constraints between the data pins and both.