anyway to improve the reliability of triple SDI rx IP

Hi rbugalho

Thank you for the reply.

To my understanding, the SDI receiver recoveries clock data, decodes bit stream from NRZI, and descrambles bit stream.

If the SDI receiver works fine, SDI receiver outputs uncompressed 20-bit video data in YUV422.

I'm studying on how to remove all the negative slacks today but have more questions about timing constraints.

For example:

1). In my design, there is an input pin connected to a button and used as a reset signal. Should I use "set_input_delay" to constrain this input? (My answer is "no" because a person can hit this reset button at anytime)

2). My design has 20 output pins for 20-bit YUV422 parallel data and a output clock pin. The clock on the output clock pin is synchronous to the data and its frequency is either 74.25MHz or 148.5MHz. Should I constrain this clock and use "set_output_delay" to constrain the 20-bit data?

Thanks.