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Altera_Forum's avatar
Altera_Forum
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8 years ago

Altsyncram mixed port width issue

Hi, Having problems generating a simple mixed dual port RAM using M10 block memory. Using Quartus 16.1.0 Build 196, for CycloneV SX (5CSXFC6D6F31C6) FPGA. Trying to generate an Oncip Memory RAM in...
clair's avatar
clair
Icon for New Contributor rankNew Contributor
7 years ago

Hi, I met the same question like you. But I do not know where to find the .byteena_a(byteenable) , would you like to tell me some details? thanks a lot!