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Honored ContributorAltsyncram mixed port width issue
Hi, Having problems generating a simple mixed dual port RAM using M10 block memory. Using Quartus 16.1.0 Build 196, for CycloneV SX (5CSXFC6D6F31C6) FPGA. Trying to generate an Oncip Memory RAM in...
Altera_ForumHonored Contributor
Honored ContributorThe table in that doc is for Arria 10. You should check the Cyclone V device handbook for the supported ratios.
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