Occasional Contributor
Regular ContributorHello,
May I know about the issue that you are facing? Is it in simulation or actual hardware?
Are you able to provide some snapshots of the problem?
Regards,
Adzim
Occasional ContributorIt's actual hardware.
Let me describe issue:
step1) write data 512 bytes from address = 0
step2) write data 512 bytes from address = 512
............................
step3) finish write data of all ddr size.
step4) read data 512 bytes from address = 0
step5) read data 512 bytes from address = 512
............................
For expectation, all read data should be the same as write one.
but sometimes, the 1~2 bytes data of 512 bytes goes different if I done below action for write process.
1. The user logic asserts the first write request to row 0 so that row 0 is open before
the next transaction.
