Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI solved the issue.
It turns out that the changing in timing was not the issue, but just a red herring. The problem was fixed by changing to the memory model created by UNIPHY. I was using the memory model from ALTMEMPHY since I couldn't get Nativelink and the flow described in the Upgrade doc to work: http://www.altera.com/literature/hb/external-memory/emi_uniphy_ref_upgrade.pdf Alternatively, I couldn't figure out how to incorporate my custom logic and testbench into the example_project/simulation that UNIPHY created.