Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Altmemphy DDR2 controller on CycIII, only mem_dq is changign

Hi All, I am quite new to Altera and FPGA design, as a small project I am trying to code a DDR2 controller on Cyclone III development board. I have used Altmemphy DDR2 megafunction, a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I guess i figured it out, thanks to support.

They told me since those mem_... signals are time critical, using them with signaltap could cause some problems, so it is better to not observe them..

And thanks for reply, I will also try to lower speed, now i m working with 166MHz and half rate for my circuit. There is only a controller in my design.