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Altera_Forum
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14 years ago

Altmemphy DDR2 controller on CycIII, only mem_dq is changign

Hi All, I am quite new to Altera and FPGA design, as a small project I am trying to code a DDR2 controller on Cyclone III development board. I have used Altmemphy DDR2 megafunction, a...
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Altera_Forum
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14 years ago

did you simulate your design ?

You can also try to reduce the speed to 133MHz or less. I had to reduce speed on an altera eval board to make my design work. The timing analysis was allowing 166MHz, the hardware was 200MHz compatible, but it didn't work at 150MHz but was ok at 133.