Honored Contributorhi,all
Now i use a ddr mem controller IP ,and this IP's interface is denalli DFI interface; but altmemphy's interface is AFI; how can i use altmemphy connect with my ddr mem controller IP in altera fpag simulation; thanks!
Honored Contributorwho can help me
Honored ContributorDo you have answer about which DFI spec. the AFI compliant with?
Honored ContributorDoes your controller use the training features of the DFI interface? If so you cant use it with AFI as AltMemPHY's calibration is enclosed within the PHY. Other than that the signals pretty much line up one to one. I think there is one extra signal left in AFI but that can easily be generated in logic.
Why do you want to use Denali controller? Could you just use Altera's controller?Honored ContributorHi,
I also use DFI controller and with a DFI PHY on an upcoming ASIC. However, we would want to verify our system in FPGA. The PHY is afterall doing something related to timing but the actual protocol verification is on the controller. I would want to verify the system with my controller but using Altera PHY. To do it, I have to interface controller DFI to AFI Altera PHY. The DFI specs I am using is DFI2.0. I use Xilinx FPGA before and able to create a DFI wrapper onto xilinx PHY but my company wanted to move to Altera. I hope the team here can assist. Can you also supply me the link to see Altera AFI specs? The controller is DDR2 now and my upcoming one is DDR3. Do Altera FPGA support DDR3 PHY ? Hope to hear from you as soon as possible. Thanks! Mr Lim
New ContributorHonored ContributorDFI is not supported by Altera, you could possibly do it with restrictions, as mentioned above.
Altera does have DDR3 PHY. 533MHz in Stratix IV AFI is documented in the EMI handbook on the web site.Honored ContributorDFI been a DDR standards by industry. Is Altera looking into making the PHY AFI? Xilinx V6 has DFI PHY. Do Altera support a DFI wrapper onto AFI interface PHY?
Honored ContributorI dont know what Altera's plans are.
Honored ContributorHow did you resolve this issue?
Honored ContributorHi all guys,
I also encounter this problem, have to connect DFI 2.0 memory controller (Denali IP core) to AFI PHY and realize it on Altera FPGA. Anyone can provide a feasible solution to resolve this problem? Thank you very much! QianHonored ContributorHere is the pin connections
control interface dfi_address => ctl_addr dfi_bank => ctl_ba dfi_cas_n => ctl_casn dfi_cke => ctl_cke dfi_cs_n => ctl_csn dfi_odt => ctl_odt dfi_ras_n => ctl_rasn dfi_reset_n => ctl_rstn dfi_we_n => ctl_wen write interface dfi_wrdata => ctl_wdata dfi_wrdata_en => ctl_wdata_valid dfi_wrdata_mask => ctl_dm Also need to add logic to generate a ctl_dqs_burst signal read interface dfi_rddata_en => ctl_doing_read dfi_rddata <= ctl_rdata dfi_rddata_valid <= ctl_rdata_valid status interface dfi_init_complete <= ctl_cal_success dfi_dram_clk_disable => ctl_mem_clk_disable for ctl_dqs_burst you need to use the dfi_wrdata_en signal but delay it depending on what sort of AFI write interface you are using. Full rate, half rate, odd or even alignment. The required waveforms are listed in Altera's external memory handbook.
