AltLVDS_RX weird data patterns

I have already done something like that. Originally, the phase difference between the clock and the data was set to 0 ps in the megafunction; then I began to increment it by the data rate duration. I stopped when all the data lines were in the correct position, and tried to fine tune it by finding the center of the data window by incrementing/decrementing the phase difference by small amounts. I didn't find a point where the data were all correct,though, just close to it.

The data is set up so when deserialized, there are predetermined values to sync to(12 from the 28 values). But because the sync signals are incorporated in the data, I deemed it was enough to set the phase shift manually in the verilog file of the megafunction(the megafunction wizard has weird values for phases, some cannot even be applied), because the relationship between the sync signals and the data will always be the same.

Did I go wrong somewhere? Is it better to set the phase difference to 0 and then rotate the data with "rx_channel_data_align"? I have written a piece of code to do just this, but then deemed it useless, because of the relationship of the data and sync signals.