Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

AltLVDS_RX weird data patterns

Hello, My problem is the following: I am using the ALTLVDS_RX megafunction on a Cyclone V, without DPA, but on the side of the FPGA where dedicated SERDES circuitry is supported(on the b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Apart from timing issues and as far as I know you, the designer, need extra logic to get word boundaries from parallel stream. i.e. you need to send a known data stream then align it until you get it back by searching through all possibilities and stop when you get the correct words