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Honored Contributor
Honored ContributorALTLVDS pins io standard
hi, I am using ALTLVDS megacore for serialization and deserialization. the serializer has tx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) and the deserializer has rx_in : IN STD_LOGIC_VECTOR ...
Altera_ForumHonored Contributor
Honored ContributorI found the reason, why Quartus doesn't accept your design.
You connected four RxLVDS instances to the same pin. This doesn't work, because Quartus needs to implement the double data rate registers as IO registers. So there can be only one RxLVDS MegaFunction for each pin. P.S.: You can disable the requirement to use IO-registers by removing the Altera synthesis attributes LVDS_RX_REGISTER=LOW and LVDS_RX_REGISTER=HIGH from RxLVDS_lvds_rx.v, which resides as a copy in the db directory. Then Quartus can use regular LE registers, but the timing will become worse, of course.
