ALTFP_SQRT IP Core data width is not 32bits

Hi,

As I understand it, you have some inquiries related to the altfp_sqrt input port witdh. For your information, I have tested generating the HDL using CV devices in Q17.0Std (because I do not have CIV device installed). As I look into the .v file, it seems like the module in your screenshot is a low level block instead of the top level altfp_sqrt module. You may scroll down to the bottom of the file and your should see something like the following which matches the IP GUI and with 32 bit data width:

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module test_sqrt (

clock,

data,

result);

input clock;

input [31:0] data;

output [31:0] result;

wire [31:0] sub_wire0;

wire [31:0] result = sub_wire0[31:0];

test_sqrt_altfp_sqrt_4jc test_sqrt_altfp_sqrt_4jc_component (

.clock (clock),

.data (data),

.result (sub_wire0));

endmodule

Please let me know if there is any concern. Thank you.