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JHill1's avatar
JHill1
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4 years ago

ALtera/Intel CIC IP non-determanistic result when selecting Hogenauer pruning

Hi,

I don't know where one might submit a bug report for the Intel FPGA IP so I submit one here.

When I configure the Intel/Altera CIC Digital Filter IP for Hogenauer pruning I noticed that the single lowest signed two's complement fixed point value produces a non-deterministic result. When I change the output-rounding option to truncation this problem vanishes.

Here is my CIC configuration.

14 input bits.

22 output bits (yes, probably optimistic).

8 stages

1 differential delay

16 decimation rate change factor

16 interfaces

1 channel per interface

Hogenauer-pruning, output rounding option

9 Replies

  • JHill1's avatar
    JHill1
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    4 years ago

    Version 17.1 of the Altera/Intel CIC IP.

  • JHill1's avatar
    JHill1
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    I tried narrowing my CIC output to 18 bits from 22 bits, but it does not fix (the problem that the single lowest signed two's complement input causes an anomalous output when Hogenauer pruning is enables in the CIC IP's output rounding option). Possibly, Intel's lookup table for the CIC IP internal number of CIC accumulator bits, is defective.

    Maybe we have no choice other than to turn off Hogenauer pruning output rounding option, and use instead now the other low resource consuming option which is truncation.

  • JHill1's avatar
    JHill1
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    4 years ago

    Ok, so the obvious solution is to artificially add one more bit to the CIC input, sign extending the two's complement fixed point by one bit, and then Hogenauer pruning CIC output rounding option can be turned back on, and the anomalous/erroneous/non-determanistic CIC output value occurring in a DC linearity test for the single most negative fixed point input value is eliminated.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Sorry for the delay. This case was just routed to me. As I read through the discussion, seems like you have managed to resolve the initial problem.


    Just would like to check with you if there is any other specific problem that I can further assist.


    Please let me know if there is any concern. Thank you.


    • JHill1's avatar
      JHill1
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago
      Maybe the CIC IP remains defective when it doesn't automatically choose sufficient number of internal accumulator bits so that an anomalous output is _not_ produced with hogenauer pruning option and for the single most negative two's complement input value, as detected when performing a DC linearity test.
      Perhaps the customer shouldn't need to add an additional (duplicated) sign bit to the CIC input to fix Altera/Intel CIC internal implementation issues?
      Alternatively, if avoiding such problems by adding an additional (duplicated) input sign bit, is seen as a user implementation choice, resource consumption trade-off, by Altera/Intel then at a minimum perhaps the single anomalous output situation should be documented in the Altera/Inte CIC manual suggesting also the possibility of adding an additional (duplicated) sign bit to the input as a workaround, from my humble perspective.
      Thanks for your interest and best regards,
      JHill1

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Thanks for your sharing. I would like to bring this to our Factory for them to look into future enhancement in IP or to the documentation. Would you mind to share with me some Modelsim simulation test case which replicate the problem observation and also the passing test case after adding your workaround. This would be helpful for the Factory to have further insight into this. Thank you very much for your help.


  • JHill1's avatar
    JHill1
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago
    Would you mind to share with me some Modelsim simulation test case which replicate the problem observation and also the passing test case after adding your workaround.

    No doubt that providing such input would speed resolution, but also this requires some effort on my part, and since I have a workaround and also a long list of other higher priority tasks that I need to accomplish, its unlikely for unfunded tasks to float to the top of my list.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Thanks for your update. I understand your concern and priorities. I would feedback the current available information to Engineering for them to look into. Thank you very much for your help.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.