Honored Contributor
ContributorHI Chafik
we are considering similar question recently. my suggestion is , please check the configuration time consumption of FPGA, if it excedd 100ms, the PC might failed to detect the downstream pcie node.
Following info quoted from xinlinx applicaiton note xapp1179, pls refer to pcie spec for more details.
The PCI Express specification states that fundamental reset must remain asserted for at least
100 ms after power becomes valid. It also states that a device must enter the detect state (be
ready for link training) 20 ms after release of the fundamental reset. Therefore, PCI Express
cores must be ready to start link training 120 ms after the power good signal. Due to legacy
reasons with PCI Express specification, this time is often referred to as the 100 ms boot time
requirement for PCI Express. In reality, the time that a PCIe core has to get ready for link
training is actually 120 ms
Welcome discussion.
