Altera Generic Tri-state Controller optimization for ZBT SRAM

Hello KWler,

I found your post very interesting. I have to manage a similar SRAM and I'm struggling with it with a similar QSys system.

I would like to ask you some question:

1) Why do you put ".sram_tcm_address_out 21 of 23 hight bits connected to SRAM Address bus" if you have only 21 bits for address? Is there a reason or you could put directly 21?

2) Why do you use only 65 MHz if your memory could work at 133 MHz? (Silly question, but maybe you have a reason to make the SRAM working at half of its maximum speed)

3) What is the type of memory are you using? The 1Mx36 or the 2Mx18 one? I can't understand it from your parameters, you chose Data width 32 but in the module assignments window you put SRAM_Data_width 16;

4) Are Parameters in the "Module Assignment" window important? I don't have a CPU or a NIOS attached (it is a straight system), if I understand well they are parameters only important for software.

5) Have you a reason to put the SRAM clock shifted? I found thin solution also in other projects and I would like to understand why.

Thank you