Forum Discussion
Altera_Forum
Honored Contributor
16 years agoMmmmhhh I have no Mathlab at my company. But I can check this at home this evening.
Referring to the input problem. I simulated the IP-core (this time with a quad-output architecture, for the reason of performance) with my test data, I attached it in form of two text files which are required by the simulation. Within the simulation, I verfied again that the sine amplitude is 30146 (first screenshot) and that the exponent is also -10 (second screenshot). (I also checked this in signaltapII) The real bin# 3 (=> 3x 2.92Hz frequency resolution = about 9Hz) has a value of 0x0D3A (with single output architecture this was 0x0D38). The imaginary bin# 3 has a value of 0xC7C7 (with single output architecture this was 0xC7C9). Look at the screenshots I attached. So the results depend on my input OR on the FFT IP-core itself and not on my processor system or my wrapper. What could be the reason for this behavior? P.S.: Thank KAZ for spending time on helping me.