Altera Avalon MM DMA controller issues in burst mode

Ok DSL ...

my only thought is the that I have been stuck there since the EP needs to be explicitly set up to perform Master ( DMA ) operations ... by setting the Master bit in the Command Register of the EP.

I'm not familiar with the block you refer to but do know the Avalon MM DMA IP has qome Quirks ... namely ... doesn't like to start on non-supported alignments and ... in burst mode desn't support transfer lenghts > Max Burst Length . You may be able to search the Altera Knowledge Base for any issues with the DMA IP you are trying to use.

M9k Block just seems to be a configurable IMEM ... the thing to be careful of here is if the data width and the DMA controller node ... in theory , I expect data width mismatches to be handled by the Avalon MM fabric, but I am not sure if the slave is 32 bits ( WORD ) and the DMA controller is set up to run in another mode like DWORD or HWORD.

ie ...

static void __pci_set_master(struct pci_dev *dev, bool enable)

1807 {

1808 u16 old_cmd, cmd;

1809

1810 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);

1811 if (enable)

1812 cmd = old_cmd | PCI_COMMAND_MASTER;

1813 else

1814 cmd = old_cmd & ~PCI_COMMAND_MASTER;

1815 if (cmd != old_cmd) {

1816 dev_dbg(&dev->dev, "%s bus mastering\n",

1817 enable ? "enabling" : "disabling");

1818 pci_write_config_word(dev, PCI_COMMAND, cmd);

1819 }

1820 dev->is_busmaster = enable;

1821 }