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Honored Contributor
Honored ContributorAltera Avalon Bus Slave interface
Hello! Simple question and straightforward: I'm building a custom IP core and want to connect it to avalon bus. This (slave) component accepts both read and write data (a master can bot...
Altera_ForumHonored Contributor
Honored ContributorBest practice is to use separate buses for logic that is internal to the FPGA as it only uses routing resources and no extra logic.
Any tristate buffers internal to the FPGA don't actually exist as tristate buffers and are synthesized into multiplexers. Good luck with designing your IP!
