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Altera_Forum
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15 years ago

ALTDDIO_OUT Megafunction: How to increase width to 1024bits wide?

For my Cyclone IV E project, is it possible to manually create a ALTDDIO_OUT instance with a width of 1024. At present, the ALTDDIO_OUT version 10.1sp1 Megafunction wizard only allows selection...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Thanks for the quick reply. You may be right about am I asking the correct question as I am very new to HDL and Altera devices and tools. I will explain further what I am trying to do.

I want to transfer a source-synchronous data packet between two Cyclone IV E on different boards. The data packet is 1024 bits and only needs to transferred every 50us or so (approx 20Mbps). Cyclone IV GX devices seem completely overkill as the SERDES runs at 600Mbps minimum and are too expensive for my application (and only come in BGA which is not suitable for our production line).

What I was trying to do was use DDR clocking on the output data line. I was looking at the Shared Material article in the forum on Implementing a Source Synchronous Interface between Altera FPGAs v2.0 (sorry the forum won't let me have a link as I am too much of a newb) for inspiration and wondering how to implement.