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NJOUB1's avatar
NJOUB1
Icon for New Contributor rankNew Contributor
7 years ago

ALTASMI_PARALLEL in full synchro design. Can I use the same clock and edge (rising edge ) for clkin and the rest of the design?

I use a ALTASMI_PARALLEL and a ALTEREMOTE_UPDATE megafunctions in a cyclone III. All the design is full synchro and use a rising edge of a 12MHz clock. I want to know if it's possible to use the same...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Nathalie,

I'm sure what is the difference between 1 and 2. ALTASMI IP sample the signals(write , wren, shift_bytes, data_in.....) on the rising edge of the clkin signal. You can just use the generate the singals base on the rising edge of the clkin signal. As far I checked internally, there are no timing constraint requirement for both ALTASMI_PARALLEL and ALTEREMOTE_UPDATE IP since these are hard block inside the device. There should not be any timing path for hard block inside the device.

Regards,

Nooraini