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Hi,
I'll try to get some hints within this thread because the content discussed here is close to my problem.
I have an Arria2GX Devkit with the EP2AGX125 FPGA. I try to implement XAUI transceiver using ALTGX, ALTGX_RECONFIG, some user logic an an external loopback adapter at the HSMC A port. The Transceivers GX8, 9, 10, 11 are used for this test.
For the short time it looks good but there are some misalignments an receive side (see attached jpgs).
According the status bits the receiver is synchronized (rx_syncstatus = X"FF") and deskewing is done (rx_channelaligned = '1'). rx_errdetect is also X"00".
Nevertheless the received date are not correct. I have verified the reset sequence, all pll_locks are like in Chapter 4: Reset Control and Power Down in Arria II Devices described.
Every new reset (or FPGA reconfiguration and reset) produces other behavior of the receivers.
The misalignment varies slightly. (2 examples attached)
What could be the problem?
Jens
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Hi
I am a beginner.
How do we check the "rx_errdetect" signal ? Do we use a oscilloscope ? Or do we use some sub-software in Quartus II to track this "rx_errdetect" signal ?
Thanks
Honored Contributor
