ALT2GXB loopback problem

I thought I would feedback some results. I put the reset logic in and the tx fifo error disappeared. I didn't quite simulate the logic but let's just assume it's working for now.

This next part is not making any sense. If I monitor the rx_freqlocked signal, it's low when the board is powered up. As soon as I connect it to the switch, it goes high. This says that it automatically switched from lock-to-reference mode to lock-to-data mode. In order to make this switch, certain conditions regarding the PLL, voltage levels have to be met.

What I did was to look at the rx_pll_locked signals on all 4 channels (pulled them out to leds). When the board is powered-up, these leds are on indicated that the rx_pll_locked[3:0] are all 0. In other words, the PLL's are not locking on the REFCLK0 which is the clock that I presume they are trying to lock onto.

So, if the PLL's aren't locking onto the REFCLK0, the how is the switch from lock-to-reference mode to lock-to-data mode begin made as the following conditions have to be met:

for automatic transition from the lock-to-reference mode to the

lock-to-data mode, the following conditions must be met:

■ the serial data at the receiver input buffer is within the prescribed

voltage signal loss threshold.

■ the cru pll is within the prescribed ppm frequency threshold

setting (62.5, 100, 125, 200, 250, 300 , 500, or 1,000 ppm) of the cru

reference clock.

■ the reference clock and cru pll output are phase matched (phases

are within approximately 0.08 ui).

Unless I have misunderstood something, I would have expected the rx_pll_locked signals all to be high in the absense of any data coming in on the rx_datain pins.

MT