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Altera_Forum
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17 years ago

ALT2GXB loopback problem

Hi, I'm using an Arria EP1AGX60CF484C6 with an ALT2GXB core configured in XAUI mode (4 lanes). I'm trying to do a loopback to test it out. The loopback is in the core, so what I've done is con...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Using the REFCLK pin will give you optimal jitter performance. you should be able to route this into the PLD for use in your logic. Quartus should choose the optimal clock resources. it will fail fitting if you do anything illegal. just try it.

Rx_Syncstatus (or I believe any of the PLLs) do not have to be asserted in order to enable loopback. Loopback is a diagnostic mode and it wouldnt be very useful if everything had to be synced up prior to it being enabled.