Honored Contributor
Honored ContributorThanks again. I'll get that calibration part hooked up.
Do you have any more information on what this actually means: "Synchronization is performed after any reset condition. You must determine when the data is valid after reset (for example, by using the rx_syncstatus signal). Table 2–52 shows the blocks affected by each reset and power-down signal." If it is done by the GXB, then I would imagine, after reset, I can't enable loopback in the FPGA until the rx_syncstatus signal is high? Is it recommended to use the pll_inclk (which is on the REFCLK0 pin) directly i.e. can I use it to drive logic? Do the tools automatically put me on clock cline or do I have to instantiate a special buffer? I want to tap the incoming PLL clock since it's always going to be on.
