Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

ALT2GXB loopback problem

Hi, I'm using an Arria EP1AGX60CF484C6 with an ALT2GXB core configured in XAUI mode (4 lanes). I'm trying to do a loopback to test it out. The loopback is in the core, so what I've done is con...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi Jake,

When you put the plug-in wizard into XAUI mode, it shows that the coreclockout is used on both the transmit side and the receive side (according to the diagram it presents). The recovered clock on the receive side is used for the first few stages then it's the coreclockout for the remainder. So the the read clock on the recieve compensation FIFO is the same as the write clock on the transmit compensation FIFO. Both the Tx PLL and the Rx PLL are fed straight from the REFCLK0 input.

MT