ALT2GXB loopback problem

I've just read the reset section and I have a few questions:

1. How long is a parallel clock cycle?

2. What does this 'Synchronization' refer to? Is this something that is done by the GXB after reset?

"Synchronization is performed after any reset condition. You must

determine when the data is valid after reset (for example, by using the

rx_syncstatus signal). Table 2–52 shows the blocks affected by each

reset and power-down signal."

If it is done by the GXB, then I would imagine, after reset, I can't enable loopback in the FPGA until the rx_syncstatus signal is high?

3. In the XAUI interface mode a coreclockout is available which I presume I can use to clock the reset logic?

Thanks