There is a whole chapter dedicated to Reset control and power down on page 2-214 of the SIIGX Handbook. "Figure 2–160. Reset Power Signal Timing Waveform" gives a typical reset sequence.
I would try implementing something like in the diagram
I would also then drive signals from your own logic into the tx_datain and associated control signals. then loopback using the conventional loopback method and verify that what you receive on the rx_dataout is the same as what you applied to Tx_datain.
If all is wotking then you should see pll_locked, rx_freqlocked, rx_syncstatus all asserted. you should also see occasional rx_patterndetect assertions (assuming your logic sends word alignement patterns etc) and also rx_ctrldetect.