Agilex7 F-Tile PMA/FEC Direct PHY IP Reconfiguration

Great questions — let me work through each of your points directly.

1. Does the standard PMA/FEC Direct PHY IP support dynamic data-rate reconfiguration?

No. The standard F-Tile PMA/FEC Direct PHY IP can be configured to support only a fixed rate, as it currently does not support dynamic rate switching. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide So if runtime data-rate changes are your requirement, you cannot meet it with the single-rate IP alone.

2. Standard Direct PHY IP vs. Multirate Direct PHY IP — which one is needed?

You need the Multirate variant. The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP enables you to use all the features and components of the F-Tile to get more bandwidth than what is available in the existing single-rate F-Tile PMA/FEC Direct PHY Intel FPGA IP. Block Description

Critically, the Multirate IP is coupled to the F-Tile Dynamic Reconfiguration Suite IP: You can currently use the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP only along with the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP. Refer to the F-Tile Dynamic Reconfiguration Design Example User Guide for quick reference on how to connect and simulate these two IPs. F-Tile PMA and FEC Direct PHY Multirate IP User Guide

Architecturally, the Multirate IP uses a profile-based model: The default base profile represents the maximum resources available in the generated IP. It is labeled Profile #0 in the GUI. Block Description Each profile defines a specific rate/fracture configuration, and the Dynamic Reconfiguration Suite IP switches between them at runtime.

3. Can the standard (single-rate) PMA/FEC Direct PHY IP be used with the F-Tile Dynamic Reconfiguration Suite IP for rate switching?

Not for data-rate switching. While the separate-soft-IP dynamic reconfiguration flow does allow instances of the standard PMA/FEC Direct PHY IP to participate in a reconfiguration group, the standard IP does not support dynamic rate switching F-Tile Architecture and PMA and FEC Direct PHY IP User Guide — so you can only reconfigure topology/fracture parameters within its fixed rate. To actually change the PMA data rate at runtime, the Multirate IP is the correct vehicle. The steps for controlling the IP with the Dynamic Reconfiguration Suite apply only when you are controlling the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP with the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP. F-Tile PMA and FEC Direct PHY Multirate IP User Guide

4. Reconfiguration procedure and key constraints

The high-level flow for Multirate IP-based dynamic reconfiguration is:

• To configure the Transceiver Toolkit for the F-Tile PMA/FEC Direct PHY Multirate IP, perform dynamic reconfiguration in your design. The Transceiver Toolkit displays the reconfiguration groups in the Select Reconfiguration Group drop-down list in the Toolkit Parameters tab. When you start System Console, the Toolkit is configured to the base starting profile. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
• You do not simply write registers to change rate — you switch profiles via the Dynamic Reconfiguration Suite IP. Each profile encodes a specific rate, fracture type, and PMA configuration. Dynamic Reconfiguration QSF settings are required, and the relevant .qsf assignments are documented in the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide. F-Tile PMA and FEC Direct PHY Multirate IP User Guide
• The IP_COLOCATE F_TILE QSF assignment is mandatory: This associates a Dynamic Reconfiguration Controller with the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP that it is controlling. The hpath1 is the hierarchy path of the F-Tile Dynamic Reconfiguration Suite IP in your design and hpath2 is the hierarchy path of the F-Tile PMA/FEC Direct PHY Multirate IP. F-Tile PMA and FEC Direct PHY Multirate IP User Guide

There are several important architectural constraints to keep in mind:

• You cannot dynamically reconfigure from one topology to another. Dynamic reconfiguration is allowed only within a topology. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
• You cannot dynamically reconfigure the F-tile system PLLs, including reference clock pin and frequency. Design Considerations
• The same System Clock PLL output must connect to all IPs within a dynamic reconfiguration group. The same topology must contain all IPs within a dynamic reconfiguration group. You must place all IPs within a dynamic reconfiguration group on the same F-tile. Dynamic Reconfiguration Rules
• All Avalon Memory-Mapped (AVMM) transactions must complete before initiating a dynamic reconfiguration operation. Pending AVMM transactions during dynamic reconfiguration can cause the AVMM interface to hang. Design Considerations

5. Example designs

The F-Tile Dynamic Reconfiguration Design Example User Guide describes the F-Tile Dynamic Reconfiguration design example generation, simulation, compilation, and hardware testing F-Tile CPRI PHY Multirate IP User Guide — this is the primary reference for a working end-to-end example. Use it in conjunction with the F-Tile PMA and FEC Direct PHY Multirate IP User Guide.

In summary: use the F-Tile PMA/FEC Direct PHY Multirate IP paired with the F-Tile Dynamic Reconfiguration Suite IP for runtime data-rate switching. The standard single-rate PMA/FEC Direct PHY IP is fixed-rate only and cannot perform dynamic rate changes regardless of what companion IP you pair it with.

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