Forum Discussion
Hi Colman,
Thank you for your feedback.
Based on your results from two boards, looks like the second board has more accurate result from the EMIF Debug Toolkit.
I want to clarify the test that you have carried out for both boards :
- The design that you have used is a same design or a different design?
- Have you tried to swap the RDIMMs between the bad(first) and good(second) boards?
- Have you tested with single EMIF interface at a time to get the calibration report?
I would need more details to debug this issue but since you have file another case in the IPS, I would like you to choose on which platform that you're comfortable continue the discussion.
Because we are usually discuss a same issue in one platform and close the other open case.
So it's depend on you if you want to discuss this issue in this forum or you want continue the discussion in IPS.
Please let me know your most convenience way.
I will take the action to facilitate this issue.
Regards,
Adzim
Hi Adzim, Let's discuss this over the IPS platform. I already uploaded more information over there.
Thanks and Best Regards,
Colman
- colm1 year ago
New Contributor
The problem is resolved and I just want to close the loop here. The root cause is that the clock driver to the EMIF reference clock was not set up correctly and caused some EMIF channels calibration failures. The confusing part was that EMIF toolkit reported calibration success, but margining info were missing. Once the clock driver is setup correctly, everything works fine.