I'm using Quartus 25.1 and have generated an example design for the GTS MCDMA targeting the Agilex 5. I'm working with the Agilex 5 FPGA E-Series 065B Modular Development Kit.I successfully generated the example design and connected all the ports to their corresponding I/Os on the FPGA, following the guidance from other example designs and the GRSD.I've noticed inconsistent behavior with the PC's detection of the PCIe card. Sometimes it's successful, and sometimes it's not. After programming a JIC file to the Agilex 5 and rebooting the PC, the PCIe device was not detected by the OS. However, while both the PC and Agilex 5 remain powered on, programming a SOF file to the Agilex and rescanning the PCI bus occasionally results in device detection, though with the following errors: Running `lspci` on the device sometimes reveals the expected details and sometimes it returns the following message: Even when the device is detected correctly, when I try to run the provided application (which is compatible with the example design), I encounter the following errors:I generated the MCDMA example design for the Agilex 7 and ran it on the Agilex 7 successfully, without any issues. I used the same application, with the necessary adjustments to match the Agilex 7 example design.Does anyone have any suggestions on how to get it working on the Agilex 5?Please find the attached QAR file.

Hi Daniel,I try to open your .qar file via quartus v25.1, it seen like the file is corrupted.Can you please re-attach ?Regards,Wincent_Altera

Hi Daniel,Next , are you using gen4 or gen3 design ?Please be aware that Gen4x4 is not supported in Agilex 5 Modular devkit, this feature will be hidden in Quartus v25.1.1 releaseWhile I am trying gen3x4 design, I able to get the device link successful - attach the design .qar (please have a try on your host)Regards,Wincent_Altera

Hi Wincent,Thanks for your quick response.It’s strange that you couldn’t open the QAR file - I was able to open it without any issues. Regardless, I’ve created a new one, which is attached to this message.Regarding your second question, I used the Gen3x4 configuration for the design.Did you make any modifications to your design beyond generating the example design?Also, do you think the issue could be related to the host system I’m using? If so, I’d appreciate any guidance on why that might be the case and how I can check for host compatibility.My host supports up to Gen5, and the Agilex 5 is powered via an external power supply rather than through the PCIe slot. I assumed that would be sufficient, but is there any other criterion that needs to be met to ensure proper functionality?Best regards,danield17

Hi Wincent,After further investigation, I noticed that in your project you selected the device number A5ED065BB32AE4SR0, whereas when selecting the modular dev kit from the board tab in the device selection menu, it defaults to A5ED065BB32AE6SR0.Is your modular dev kit different from the default one, or is it normal that the board’s default device number isn’t always the one we should use?How can I verify which device I should be working with? So far, I have been using A5ED065BB32AE6SR0 and was able to program the FPGA, but could that be incorrect?Regards,danield17

Hi Daniel,Sorry for taking 4 days to reply this, I miss out your reply in last week and over the weekend..Did you make any modifications to your design beyond generating the example design?>> Generate the Design Example by default without changing anything >> One thing i change is on the design example tab where I select the "target devkit" it help to assign all pin assignment accordingly on the Modular Devkit>> Also, do you think the issue could be related to the host system I’m using? If so, I’d appreciate any guidance on why that might be the case and how I can check for host compatibility.>> Based on my experience of working on PCIe, certain host having problem to direct perform speed degrade if the PCIe Speed on BIOS setting is selected as "AUTO" , perhaps you can try to select "GEN3" same as your design and check if this work or not. >> this method work for me in most of the previous device (Arria 10, Stratix 10)I noticed that in your project you selected the device number A5ED065BB32AE4SR0, whereas when selecting the modular dev kit from the board tab in the device selection menu, it defaults to A5ED065BB32AE6SR0. Is your modular dev kit different from the default one, or is it normal that the board’s default device number isn’t always the one we should use?>> My devkit is the normal one with OPN A5ED065BB32AE6SR0 https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-modular.html>> I believe it is default setting if I select the "current development kit" in IP GUI during Design Example Generation>> Anyway the .sof passing 100 % upon programming>> the "4s" and "6s" represent the speed grade of PCIe, where the "4s" would be the fastest one (supporting gen4)>> Did you try my .qar file ? is it work on your side ?Regards,Wincent_Altera

Agilex 5 MCDMA Example Design Identification Issues

11 Replies

Wincent_Altera
Regular Contributor
8 months ago
Hi Daniel,
I try to open your .qar file via quartus v25.1, it seen like the file is corrupted.
Can you please re-attach ?
Regards,
Wincent_Altera
- Wincent_Altera
  Regular Contributor
  8 months ago
  Hi Daniel,
  
  Next , are you using gen4 or gen3 design ?
  Please be aware that Gen4x4 is not supported in Agilex 5 Modular devkit, this feature will be hidden in Quartus v25.1.1 release
  
  While I am trying gen3x4 design, I able to get the device link successful - attach the design .qar (please have a try on your host)
  
  Regards,
  Wincent_Altera
  pcie_ed_25_1_0_129.7z23.8 MB
  - danield17
    New Contributor
    8 months ago
    Hi Wincent,
    Thanks for your quick response.
    It’s strange that you couldn’t open the QAR file - I was able to open it without any issues. Regardless, I’ve created a new one, which is attached to this message.
    Regarding your second question, I used the Gen3x4 configuration for the design.
    Did you make any modifications to your design beyond generating the example design?
    Also, do you think the issue could be related to the host system I’m using? If so, I’d appreciate any guidance on why that might be the case and how I can check for host compatibility.
    My host supports up to Gen5, and the Agilex 5 is powered via an external power supply rather than through the PCIe slot. I assumed that would be sufficient, but is there any other criterion that needs to be met to ensure proper functionality?
    Best regards,
    danield17
    pcie_ed_25_1_0_129.qar14.3 MB
Wincent_Altera
Regular Contributor
7 months ago
Hi,

I wish to follow up with you about this forum thread.
Do you have any further questions on this matter ?

Regards,
Wincent_Altera
- danield17
  New Contributor
  7 months ago
  Hi Wincent,
  
  From what I understand, the plan for now is to wait for the user guide to be released.
  I don’t have any other questions at the moment, and I really appreciate your help and patience.
  
  Best regards,
  danield17
  - Wincent_Altera
    Regular Contributor
    7 months ago
    Hi Daniel,
    
    You are most welcome, glad to work with you as well.
    The user guide is in final stage, it is going to be release within 1-2 weeks from now.
    Upon the release of the userguide, I will personal try all the step as well.
    
    If you facing any problem, you can just file a new thread.
    IF you need specifically my support, you can just mentioned my name "Wincent" to the thread.
    I will be full commitment to assist you further.
    
    Wish you have a nice day.
    
    Regards,
    Wincent_Altera

Forum Discussion

Agilex 5 MCDMA Example Design Identification Issues

11 Replies

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