Forum Discussion

danield17's avatar
danield17
Icon for New Contributor rankNew Contributor
8 months ago

Agilex 5 MCDMA Example Design Identification Issues

I'm using Quartus 25.1 and have generated an example design for the GTS MCDMA targeting the Agilex 5. I'm working with the Agilex 5 FPGA E-Series 065B Modular Development Kit. I successfully generat...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
8 months ago

Hi Daniel,

I try to open your .qar file via quartus v25.1, it seen like the file is corrupted.

Can you please re-attach ?

Regards,

Wincent_Altera

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    8 months ago

    Hi Daniel,

    Next , are you using gen4 or gen3 design ?
    Please be aware that Gen4x4 is not supported in Agilex 5 Modular devkit, this feature will be hidden in Quartus v25.1.1 release

    While I am trying gen3x4 design, I able to get the device link successful - attach the design .qar (please have a try on your host)


    Regards,

    Wincent_Altera

    • danield17's avatar
      danield17
      Icon for New Contributor rankNew Contributor
      8 months ago

      Hi Wincent,

      Thanks for your quick response.

      It’s strange that you couldn’t open the QAR file - I was able to open it without any issues. Regardless, I’ve created a new one, which is attached to this message.

      Regarding your second question, I used the Gen3x4 configuration for the design.

      Did you make any modifications to your design beyond generating the example design?

      Also, do you think the issue could be related to the host system I’m using? If so, I’d appreciate any guidance on why that might be the case and how I can check for host compatibility.

      My host supports up to Gen5, and the Agilex 5 is powered via an external power supply rather than through the PCIe slot. I assumed that would be sufficient, but is there any other criterion that needs to be met to ensure proper functionality?

      Best regards,
      danield17

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        7 months ago

        Hi Daniel,

        Sorry for taking 4 days to reply this, I miss out your reply in last week and over the weekend..

        Did you make any modifications to your design beyond generating the example design?
        >> Generate the Design Example by default without changing anything
        >> One thing i change is on the design example tab where I select the "target devkit" it help to assign all pin assignment accordingly on the Modular Devkit
        >>


        Also, do you think the issue could be related to the host system I’m using? If so, I’d appreciate any guidance on why that might be the case and how I can check for host compatibility.
        >> Based on my experience of working on PCIe, certain host having problem to direct perform speed degrade if the PCIe Speed on BIOS setting is selected as "AUTO" , perhaps you can try to select "GEN3" same as your design and check if this work or not.
        >> this method work for me in most of the previous device (Arria 10, Stratix 10)

        I noticed that in your project you selected the device number A5ED065BB32AE4SR0, whereas when selecting the modular dev kit from the board tab in the device selection menu, it defaults to A5ED065BB32AE6SR0. Is your modular dev kit different from the default one, or is it normal that the board’s default device number isn’t always the one we should use?
        >> My devkit is the normal one with OPN A5ED065BB32AE6SR0 https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-modular.html
        >> I believe it is default setting if I select the "current development kit" in IP GUI during Design Example Generation
        >> Anyway the .sof passing 100 % upon programming
        >> the "4s" and "6s" represent the speed grade of PCIe, where the "4s" would be the fastest one (supporting gen4)
        >> Did you try my .qar file ? is it work on your side ?

        Regards,
        Wincent_Altera

    • danield17's avatar
      danield17
      Icon for New Contributor rankNew Contributor
      7 months ago

      Hi Wincent,

      After further investigation, I noticed that in your project you selected the device number A5ED065BB32AE4SR0, whereas when selecting the modular dev kit from the board tab in the device selection menu, it defaults to A5ED065BB32AE6SR0.

      Is your modular dev kit different from the default one, or is it normal that the board’s default device number isn’t always the one we should use?
      How can I verify which device I should be working with? So far, I have been using A5ED065BB32AE6SR0 and was able to program the FPGA, but could that be incorrect?

      Regards,
      danield17