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Altera_Forum's avatar
Altera_Forum
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18 years ago

address alignment during master write bursts?

Moin, Have some strange behaviour right here: I'm using QII6.1 and the CyclonII-NIOS-Evalboard; have built a sopc containing (besides other things) a PLL generating the clock of 85MHz, NIOS...
Altera_Forum's avatar
Altera_Forum
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18 years ago

I would expect the problem still exists with the SDR as well.

The boundaries vary however. For DDR2 the native burst length is 2, for DDR it's 4 and I believe for SDR it's 4. So where the problem shows up, is depended on the native burst length, but I believe it exists for all of them.

Pete