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Altera_Forum
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18 years ago

address alignment during master write bursts?

Moin, Have some strange behaviour right here: I'm using QII6.1 and the CyclonII-NIOS-Evalboard; have built a sopc containing (besides other things) a PLL generating the clock of 85MHz, NIOS...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Moin,

Thanks for the hints, i'll have a look into the SRDAM datasheet.

So i might assume that i'll have less difficulties with bursting when i switch from DDR-SDRAM (i currently have to use on the NIOSII-Eval-Board) to SDR-SDRAM (i plan to use on my own HW-Design).

Cheers,

WK