address alignment during master write bursts?

Hi Sledghedge post is exactly correct:

When you do burst transfers to the the DDR2 controller, the burst fabric doens't break up the burst based on the DDR2 burst limitation, so unaligned bursts will give you this problem.

This problem changes based on what type of RAM you are talking too. DDR and DDR2 have different native burst lengths, but I believe the problem exists for all of them.

(I know for sure it exists for DDR2)

We had to correct this problem in each of our master devices. However, if you are willing to attempt it, there is a generated file usually called burst0.v, that can be modified to fix the alignment issue.

The problem with fixing it this way, is it is generated every time you modify your SOPC system, so you either have to update the script (At your own risk) that generates the burst0.v or remember to copy the fix after every SOPC generation.

I really wish Altera would fix this issue, because it is a performance killer when doing video warping.

But they claim it's a limitation of the DDR2 not the burst system, but they also don't document this issue anywhere.

Regards.

Pete