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Honored Contributor
Honored Contributoraddress alignment during master write bursts?
Moin, Have some strange behaviour right here: I'm using QII6.1 and the CyclonII-NIOS-Evalboard; have built a sopc containing (besides other things) a PLL generating the clock of 85MHz, NIOS...
Altera_ForumHonored Contributor
Honored ContributorI had a similar issue about a year ago, this may not be 100% correct, but when you burst into DDR2 it will do a essentially a cache wrap, take a look in the DDR data sheet it should talk about it. THe DDR core and SOPC do not honor this, i.e. it assumes linear addressing.
