Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

address alignment during master write bursts?

Moin, Have some strange behaviour right here: I'm using QII6.1 and the CyclonII-NIOS-Evalboard; have built a sopc containing (besides other things) a PLL generating the clock of 85MHz, NIOS...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I had a similar issue about a year ago, this may not be 100% correct, but when you burst into DDR2 it will do a essentially a cache wrap, take a look in the DDR data sheet it should talk about it. THe DDR core and SOPC do not honor this, i.e. it assumes linear addressing.