address alignment during master write bursts?

Moin,

Hmmm, not much response yet: Nobody else having such kind of problems? Or is the solution much too obvious to post here? :)

I've solved it so far by using an initial burst with length 1-3 (or no initial burst, if the address ist already aligned) and then proceeding with 16xfer bursts, but i would feel much better if i'd had some specification somewhere, describing the burst abilities of avalon components.

Cheers

WK