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Altera_Forum
Honored Contributor
Honored ContributorAdder-Multiplier -> FIR IP trade-offs
Hi, I am a few months in to building a data acquisition system on a DE1 board (for prototyping) and have written a FIR filter using VHDL. I have noticed that Altera provides the megafunctions for FIR...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- any recommendations? --- Quote End --- Yes, read about MACC filters - that is what you are designing. The Xilinx Virtex-4 Xtreme DSP guide has a pretty good description. The Microsemi DSP guide (for the SmartFusion2/Igloo2) also goes over this architecture. I don't recall if I ever found a good Altera example. The Stratix Cookbook might have an example. The trick is to use RAMs for the coefficient storage and input samples. You can also exploit symmetry, eg., even symmetry of taps can be exploited using a preadder. That should give you enough hints. If you get stuck, ask for more help. Cheers, Dave
