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Altera_Forum
Honored Contributor
Honored ContributorAdder-Multiplier -> FIR IP trade-offs
Hi, I am a few months in to building a data acquisition system on a DE1 board (for prototyping) and have written a FIR filter using VHDL. I have noticed that Altera provides the megafunctions for FIR...
Altera_ForumHonored Contributor
Honored ContributorAhhh ya gotcha...cool, so if i understand you right: your saying that i just fetch a coefficient on every clock cycle multiply it, accumulate the result, and recycle the routine through the set of taps all before the next data sample arrives for convolution? 1562 taps would give me a great cutoff as well!
