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Altera_Forum
Honored Contributor
Honored ContributorAdder-Multiplier -> FIR IP trade-offs
Hi, I am a few months in to building a data acquisition system on a DE1 board (for prototyping) and have written a FIR filter using VHDL. I have noticed that Altera provides the megafunctions for FIR...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi Kaz, nice to meet you and thank you for your insight (ill look into those avenues further). The sampling rate should be around 32k, my clock is 50MHz, I had previously written a simple moving average (attached) based on (file:///C:/Users/Owner/Downloads/06_MVD_%20FIR_Design%20(12).pdf), with the idea that i could simply load coefficients in for the impulse response. Originally i wanted to use a microprocessor to calculate a filter coefficients automatically using Parks-Mcclellan, but that appears to be a long way off from where I'm at currently(still pretty green). http://www.alteraforum.com/forum/attachment.php?attachmentid=13113&stc=1 --- Quote End --- Hi, A clock rate of 50MHz and signal rate of 32K means a ratio of 1562. So you can run 1562 taps on single multiplier as multiply accumulate-reset. Isn't that enough for your filtering?
