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Altera_Forum's avatar
Altera_Forum
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9 years ago

ADC IP Core Issue

Hi,

I'm trying to implement an ADC core with the core variant as ADC control core only in MAX10. I enabled the debug path for ADC1 as well as CH 0 of ADC1. In Qsys I made all the connections as required and created a block diagram and connected the Clock and the reset pin to PIN_M9 and PIN_L22 respectively. When launching the ADC toolkit the Sampling Rate is automatically set to 999 Hz whereas I set the sampling rate during the ADC configuration to 1 MHz. Also on clicking the Run button no data is being captured in the Scope tab. I have attached the screenshot of the ADC configuration as well as ADC toolkit. Is there any other configuration that I need to set up for using the ADC in ADC control core only ?

Thanks,

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Have you checked that you are feeding in a clock signal? And that you are not holding the system in reset.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi TCWORLD,

    I connected the clock to the PIN_M9 and the Reset to PIN_L22 and have also checked that the clock is available. Is there any other configuration that I need to do while using the ADC in ADC Control Core variant ?

    Thanks,