Forum Discussion
Altera_Forum
Honored Contributor
15 years agoAssuming that reply was not cynical (I was trying to answer your question exactly as you asked it...)
Note that sclr signals generate muxes on the data input of flipflops. Thats how (or one way) the clear is made synchronous. aclr works more directly internal to the Flip-Flop ...read up about J-K and RS flip flops to understand more about their internal workings. Also note that aclr signals tend to become global nets whereas sclr signals do not have to be. Global signals are a a precious resource. I would suggest that if you have an external reset signal or even a power up reset signal ... have this signal logically ANDed with the lock output of the clock being used and pass this through at least two flip-flops. Assign the signal on the output of the last flip-flop to be global and use this as your aclr in the design. Lots of reasons related to the previously mentioned digital synchronous design requirements of setup, and hold for this. Lastly ... dont forget that typical statemachines are also synchronous processes... easy to forget that. The first state can become an asynchronous state if poorly designed...and this can lead to violations of setup and holds on signals that transition when leaving this state. Be carteful with statemachines. If you resync the aclr global as previously mentioned you will be fine. I hope this helps. Good luck